Surface finishing in many arts may utilize polishing and/or planarization. As used herein the term "polishing" shall include polishing and/or planarization. Polishing is of particular importance in the manufacturing of semiconductor devices. The concentration of integrated circuit components included on a semiconductor chip is continually increasing. Concentration may be increased by decreasing component size. As component size decreases, surfaces on which components are formed should be increasingly smooth to produce desired component configurations and thereby reduce failure rates and increase product yield. Therefore, the effectiveness of polishing fluids has significant impact on the quality of integrated circuits produced.
Semiconductor devices typically comprise multiple layers, throughout which are incorporated integrated circuits. Integrated circuit features and components, which may vary in height, are typically created by lithographic processes on each layer. Height variations contained on one layer may present themselves on subsequent layers creating nonplanar layer surfaces. Such surface irregularities may be problematic in lithographic processes used to form additional circuit components. Therefore, it is desirable to perform lithographic processes only on substantially smooth, planar surfaces.
A typical semiconductor device fabrication lithographic process includes depositing a radiation sensitive material or resist on a surface, exposing the resist to radiation through a mask to transfer a desired pattern onto the surface, and developing the resist to reveal the exposed pattern. Typically, if a resist is deposited on an irregular surface, it will have a corresponding irregularity. Such irregularities may cause variations in a depth of focus across the device so that pattern features may not be brought uniformly into sharp focus. If portions of the surface are not in focus, the pattern may not be accurately transferred.
Additionally, surface irregularities may adversely affect device interconnect reliability because metal layers deposited over a surface irregularity may acquire unwanted configurations. These configurations may cause undesirable current crowding in metal layers. For the above reasons polishing is an important step in semiconductor device fabrication processes.
Chemical-mechanical polishing (CMP) is a technique widely used in the fabrication of semiconductor devices. CMP is performed by introducing a polishing fluid or slurry between a workpiece surface and a polishing article and moving the article and device relative to one another. The slurry generally comprises abrasive particles which may mechanically and chemically wear down unwanted surface irregularities. Additional constituents chemically react with the workpiece surface to smooth and planarize it. A polishing article, such as a polishing pad may also mechanically wear away surface irregularities.
CMP reaction products may become imbedded in the surface which is being polished, and may cause scratches, particle defects and impurities in surfaces. For example, during copper CMP, traces of copper and barrier metal may be seen in the oxide dielectric layer. Defects, scratches and impurities may reduce the reliability of the device. It is known in the art to utilize chemical solutions such as hydrofluoric acid (HF) to clean a surface after CMP to reduce adverse effects of reaction products. Although generally helpful in removing reaction products, such solutions may etch away a portion of the layer that was polished. Additionally, planarity or smoothness may be degraded by such post-CMP processes because of step generations caused by dielectric oxide removal. Furthermore, solutions such as HF used in copper CMP may attack barrier films causing localized corrosion in copper trenches. Therefore, it is desirable to develop a polishing fluid and method that remove reaction products from the surface being polished without damaging the polished layer.